Having looked at magnetic and optical storage media, John Watkinson turns to electronic memory with the emphasis on flash.
Magnetic and optical media are what they are and they have to operate using mechanical scanning. Electronic memory is somewhat different in that variations on the technology and the addressing mechanism have been developed according to the application.
For example, the goal of a cache memory is to be blisteringly fast, so the processor doesn't wait for main memory so often. The cache is not large, so the cost per bit isn't too important, and it doesn't matter if the data are lost when the machine is turned off. On the other hand a lot of memory applications, such as the BIOS of a programmable machine, require the data to be non-volatile, but no great speed is needed as it is only used once at startup.
Whilst optical and magnetic storage devices are fundamentally block-based and serial in nature, electronic memory can be organized in various ways. If necessary, individual bytes can be accessed in a true random access structure. On the other hand it may be more economical to organize the memory such that it can only be accessed in blocks.
The basic principle of non-volatile memory is very simple. If a conductor is completely surrounded by insulating material, any electrons on that conductor are trapped indefinitely. The number of trapped electrons determines the charge. If that charge is quantized, then m-ary data may be stored.
If the basic principle is simple, there are still a couple of problems that are not so simple, and both follow from the fact that the electrons are trapped. The first one is to know how much charge is trapped so that the cell can be read. The second one is harder. If the electrons are perfectly insulated, how is the charge to be changed so the cell can be written?
The charge trapped in the cell is measured using the field effect. The electrons can't escape from the cell, but their electric field can pass through the insulation. Electric fields don't penetrate into conductors such as metals, but they can penetrate semiconductors, in which the field changes the conductivity. In the field effect transistor, the conductivity of a channel between the source and the drain is modulated by voltage on the insulated gate.
A memory cell is like a field effect transistor in which there is an extra gate that is not connected to anything, hence the term floating gate. Fig.1 shows that above the floating gate there is another electrode. The trapped charge on the floating gate reduces the ability of the top electrode to cause current to flow in the channel. For that reason, the presence of charge in the floating gate is considered to represent a logical 0. In order to read the cell, a voltage is applied across the channel and another is applied to the top electrode. If the floating gate has few electrons, the top electrode will be able to make a channel current flow, so the state of the floating gate will be read as a 1, without changing it.
Fig.1 A memory cell is basically a MOSFET with a floating gate under the usual gate. Electrons in the floating gate are considered to represent a binary 0. When a cell is erased by the removal of electrons, it is set to 1. The source line grounds the MOSFET, the word line enables it, and the bit line will be pulled down as a function of the stored charge.
One technique used to get electrons into or out of the floating gate cannot be explained by classical physics, because it is a quantum effect. In a classical electrical circuit, discrete electrons cannot proceed past an insulator. However on the small scales at which quantum mechanics operates, an electron isn't really a discrete entity anymore. It is a wave function that doesn't have a known location. The best that can be said about the location is that it follows a statistical distribution.
A classical insulator of classical dimensions is unimpressed by that, but when the dimensions of the insulator become very small, as they can in microelectronics, the insulating layer may be smaller than the distribution function, so there is a finite probability that the electron could be on either side of the insulator. Driven by a relatively low voltage, electrons can actually get in to the insulated gate from the channel by a quantum mechanical process called tunneling.
The very thin insulating layers used in electronics mean that very large field strengths can be obtained with moderate voltage. A carrier that has obtained enough energy from the field can punch through the insulation in a mechanism called hot carrier injection. The insulation does not necessarily benefit from the process, and puts a finite limit on the number of times the device can be written.
The EPROM was the first ROM that could be programmed using hot carrier injection to get charge into the floating gates, but there was then no electrical way to get the charge out again, and these devices had to be erased using ultraviolet light, which ionized the insulating layer so the charge could leak out. The chip could be recognized from a transparent window that allowed the light in when erasing.
Later devices such as flash memory use tunneling, which is easier on the insulation.
Fig.2 NOR type memory cells are connected in parallel. One word line is enabled at a time and the state of the selected cell appears on the bit line.
A given floating gate that stores one bit needs associated bits and pieces to select, write and read it. Most of the differences between types of memory relate to how those processes are achieved. For example an EEPROM can change individual bytes and needs complicated erase circuitry to do that, whereas a flash memory erases entire blocks at once with one transistor. That is the main distinction between EEPROM and flash. The lower cost per bit and higher density of flash turns it into a block based storage medium like optical and magnetic storage.
Each cell in a flash memory is essentially a logic gate, because the stored bit controls the channel current only when the gate is enabled. Logic gate terminology is used to describe the way that memory cells are arranged and accessed.
Fig.2 shows an arrangement in which a number of cells have their sources grounded and the drains are connected in parallel to a bit line. Word lines run at right angles connecting the gates. Only one word line can be enabled at a time, and if the selected cell is a 1, the bit line will be pulled low. The arrangement of paralleled transistors, any one of which can pull the output low, resembles the structure of a NOR gate.
The NOR structure allows freedom of addressing, but it comes at the cost of providing a ground connection and a bit line to every cell, and that uses up area on the chip. The alternative, shown in Fig.3, is to dispense with the ground wiring by connecting memory cells in series in long strings. The string will only conduct and pull the bit line low when every cell is on. The structure is therefore like a NAND gate.
Fig.3 NAND type memory puts cells in series, reducing the number of connections and increasing superficial density. One string of series bits is connected to the bit line by a pair of select transistors and then one-word line is enabled at a time so the bit values appear serially on the bit line.
In order to select the bit to be read, the gates of all but the selected cell are set to a higher than usual voltage that causes the cells to turn on whatever their bit state. Only the selected cell receives the normal gate signal so that the state of charge in the floating gate controls the bit line.
With the cells in a string connected in series, it should be clear that they have to be read sequentially, so the bit line develops a serial data stream. That is exactly what comes out of a magnetic or optical drive, so the NAND architecture is ideal for mass storage applications, where the elimination of tracks on the chip increases storage density.
While the intersection of the word and bit lines address an individual bit to set it to 0 by pulling electrons into the floating gate, that approach can’t be used to set it back to 1 as this requires the word line to go to zero volts, when it can no longer enable a cell. The solution is that if any bits programmed to 0 need to be changed to 1, the cells need to be erased to all 1s first and then the 0s are re-programmed.
Erasure is done by taking all of the word lines to zero volts, which means that every cell addressed by those word lines will be erased. It is fundamental to the operation of NAND flash memory that re-writing has to be preceded by the erase of a whole block in a read-erase-write cycle.
Erasing is significantly slower than reading or writing. In practice read-modify-write may be used instead, where the modified data are written in a new location and the old location is flagged as invalid. This may happen as part of a wear leveling process. This extends the life of the device because writing is spread over the whole memory instead of being concentrated in one place.
Most of these processes are invisible to the host device and the only evidence is where a transaction takes longer than usual because an erase could not be avoided.
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