What You Need To Know About Return Loss

SMPTE defines a set of stringent requirements for return loss, which have been challenging for many hardware designers even at today’s speed of 2.97 Gbps. As the industry upgrades to 5.94 Gbps and 11.88 Gbps to support ultra-HD video resolutions, meeting return loss will become even more challenging.

In the professional video industry, return loss is an important parameter that measures the reflected signal that bounces back from a terminated device. This Texas Instruments article discusses return loss in general, the SMPTE requirements and why they are challenging, the design methodology including board layout optimization through co-simulations, and new video solutions that help users in solving these challenges.

In a communication system, insertion loss is a common term used to describe the signal loss in the system. Return loss is an equally important parameter that measures the reflected signal that bounces back from a terminated device. In an ideal world with perfect device termination, there is no reflected signal, and the return loss is infinite. In a system with poor return loss, the level of reflected signal will negatively impact the signal fidelity of the transmitted signal.

What is return loss

Return loss is a mathematical term to measure how well a device’s termination matches with its target impedance, which also indicates the amount of reflected signal. In the video world, the target impedance is 75 Ω for matching the characteristic impedance of the coaxial cable used in signal transmission. In the real world, due to the tolerance of the termination resistor and its parasitic elements (both inductance and capacitance), the termination is never perfect and varies with frequency. Figure 1 illustrates the return loss definition, and Figure 2 shows the return loss of the termination.

Figure 1: Return loss definition for a terminated port

Figure 1: Return loss definition for a terminated port

Figure 2: Return loss plot for the terminated port

Figure 2: Return loss plot for the terminated port

Let us examine a simplified circuit of a video link shown in Figure 3. The impedance looking into the Bayonet Neill-Concelman (BNC) connector port of the transmitter or receiver is expected to be 75 Ω. In the transmitter and receiver integrated circuits (ICs), the electromagnetic discharge (ESD) protection structure presents a parasitic capacitance that shunts the 75 Ω termination. The impedance drops at high frequency and degrades the return loss. Figure 4 shows that the return loss of the circuit is unable to meet the return loss requirements defined by the Society of Motion Picture and Television Engineers (SMPTE).

Figure 3: Simplified diagram of a video link

Figure 3: Simplified diagram of a video link

Figure 4: Return loss of the video receiver

Figure 4: Return loss of the video receiver

Solving the return loss challenge

A common method to solve the return loss challenge is to add a series network that counter-balances the impedance drop caused by the parasitic capacitance of an integrated circuit. Figure 5 shows the return loss compensation network consisting of L-R elements that offsets the impedance drop caused by CIN of the integrated circuit. Figure 6 shows the ideal return loss after adding the return loss network. This compensation technique is commonly used in video circuits designed for serial digital interface (SDI).

The return loss compensation network also forms a low-pass filter that decreases signal bandwidth and adds jitter. Therefore, the user has to design the compensation network to meet return loss with a good margin, while not adding too much jitter that adversely affects signal integrity.

Figure 5: Simplified diagram of receiver with return loss network

Figure 5: Simplified diagram of receiver with return loss network

Figure 6: A receiver’s return loss after using return loss network

Figure 6: A receiver’s return loss after using return loss network

How to optimize return loss

In a real implementation of the video circuit, there are circuit elements such as the printed circuit board (PCB) trace, alternating current (AC) coupling capacitors, BNC connector, as well as parasitics of the components and their PCB footprints. These elements, along with the placement location of the compensation network, all play a role in affecting the return loss of the circuit. Figure 7 illustrates the equivalent circuit of a typical video input port, including the parasitic elements.

With the PCB parasitic and placement constraints, Figure 8 illustrates the return loss of a poorly designed receiver, despite the return loss network being used. In order to meet the SMPTE return loss specifications, designers should optimize the components’ PCB footprints, the value and the location of the return loss network, and their parasitics in a high-speed PCB design. Table 1 lists a few recommendations as guidance in the optimization process.

Figure 7: Simplified circuit showing PCB parasitic elements

Figure 7: Simplified circuit showing PCB parasitic elements

Figure 8: Return loss of a receiver without optimizing PCB parasitic

Figure 8: Return loss of a receiver without optimizing PCB parasitic

Table 1: Return loss optimization recommendations

Table 1: Return loss optimization recommendations

Upgrading to 11.88 Gbps UHD

Over the years, video resolutions have moved from 270 Mbps standard definition (SD), to 1.485 Gbps high definition (HD), to 3 Gbps widely used today. Optimizing return loss is a challenging task at increasingly higher speeds. With the industry upgrading to 11.88 Gbps ultra high-definition (UHD) supporting display resolutions of 4K/8K, it is even more challenging to meet the stringent return loss specifications. The IC’s ESD capacitance becomes more dominant and the parasitic effect of external components is more difficult to optimize at higher frequencies.

Texas Instruments offers a new class of video integrated circuits with on-chip 75 Ω termination and return loss compensation network. By following simple design methodology recommended in below paragraphs, these integrated circuits assist system designers in upgrading to a new class of UHD equipment with little worry in meeting the stringent return loss specifications.

Figure 9: New 11.88 Gbps UHD video IC simplifies return loss design

Figure 9: New 11.88 Gbps UHD video IC simplifies return loss design

Choosing a PCB board stack-up

In a typical video sub-system, a digital video signal is routed from a BNC connector through an AC-coupling capacitor to a high-speed video IC with 75 Ω single-ended trace. The video IC also interfaces to an FPGA or video processor through 100 Ω coupled traces. A board stack-up is chosen to allow the 75 Ω and 100 Ω trace routing with 6-10 mils trace widths, minimizing insertion loss and impedance mismatch.

Figure 10 illustrates an example of the PCB layout, while Figure 11 shows the cross-sectional view of the PCB stack-up. In this example, the 100 Ω differential traces are routed with 8-mil trace widths, separated by a gap of 10 mils, and achieve 100-Ω differential impedance with reference to the ground plane at layer 2. The 75 Ω single-ended trace is also routed with an 8-mil trace width, and achieves 75-Ω characteristic impedance with reference to the ground island placed at layer 3.

The landing pads of the BNC and the AC-coupling capacitor have larger widths than the 8-mil traces, resulting in a large impedance drop from the 75 Ω target and impacting return loss. Anti-pads are used as remedies, as shown in Figure 10 and 11. The metal in the ground planes below the landing pads is removed, effectively increasing the dielectric distance, reducing the parasitic capacitance and raising the impedance of the landing pads. With the proper anti-pad size, it is possible to design the impedance of the landing pads to match the trace impedance.

Figure 10. Top-view of a PCB layout showing layers 1-3

Figure 10. Top-view of a PCB layout showing layers 1-3

Figure 11. Cross-sectional view of the PCB stack-up

Figure 11. Cross-sectional view of the PCB stack-up

Return loss design methodology

Once you choose the PCB stack-up, a quick pre-layout simulation allows you to design with confidence and avoid costly board re-design. A 2 ½-D electromagnetic field solver offers fast simulation time that is most suitable for running what-if simulations in a PCB optimization analysis.

A co-design simulation involves four elements:

  1. The mated BNC model including the effect of the BNC connector and BNC footprint, usually provided by the BNC supplier in the form of an s-parameter model.
  2. The PCB structures, including the trace length, width and the board’s material properties. The landing pad is conveniently modeled with a different set of material properties in order to emulate the pad’s impedance. As an example, the landing pad can be modelled to have an impedance of 65 Ω assuming an anti-pad is used.
  3. The AC-coupling capacitor’s non-ideal model, provided by the capacitor’s supplier.
  4. The video IC’s input or output model, provided by the IC’s supplier, usually in the form of lumped element model (R, L and C), or in the form of an s-parameter model.

A three-dimensional (3-D) electromagnetic simulator is used to simulate the landing pad structure used for determining the anti-pad size in order to achieve the pre-determined target impedance (in this example, better than 65 Ω). Running 3D simulations on a small landing pad structure is much faster than running a larger board simulation, which usually takes days. For more accurate results, a final post-layout simulation based on the actual board layout is highly recommended.

Conclusion

Meeting SMPTE return loss requirements is historically challenging in the video world, relying on external termination and a return loss compensation network that leaves the challenge to system designers on complex iterative board optimization. When upgrading to UHD, it is not practical for optimizing external components on return loss and other SMPTE parameters, such as jitter and signal edge rates. Texas Instrument’s advanced circuit design and process technology offer new video solutions with integrated termination and an integrated return loss compensation network. This new class of semiconductor solutions, in combination with common high-speed board design methodology, gives system designers the ability to upgrade equipment to 11.88-Gbps UHD with confidence in meeting stringent SMPTE requirements. These new video solutions are key elements in bringing UHD live broadcasts to the consumer’s home.

Additional resources

About the author

Alan Tsun-kit (T.K.) Chin is a systems and applications manager with TI’s Signal and Datapath Solutions business unit where his current responsibilities include product definition, silicon validation and applications support for high-speed interface products for broadcast video, compute and infrastructure markets. T.K. supports a wide range of data communication interface products including equalizers, redrivers, retimers and SerDes ICs. T.K. received his BEng degree from Hong Kong Polytechnic. He has been awarded seven U.S. patents in the data communication field.

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