Deliver High Quality/High Performance HEVC via Intel Media Server Studio

HEVC is an exciting, cutting edge, highly efficient, new video compression technology enabling next generation of digital media applications, products and services. Intel is at the forefront of this development, leading the transition to HEVC technology through both hardware and software. Intel Media Server Studio aims to offer industry leading, among the best in the class developer focused HEVC technology with the best tradeoff of quality versus performance. This paper introduces the capabilities of Intel’s developer HEVC product offering, the Intel Media Server Studio HEVC Encoder and Decoder, which now packs support for coding of 4:2:0 8-bit, 4:2:0 10 bit, 4:2:2 8-bit, and 4:2:2 10-bit content. The paper also identifies various opportunities in applications, services, ecosystems, and devices that result from unleashing of powerful, high quality, high performance HEVC-based solutions.


HEVC or H.265 is a new, highly efficient, video compression standard from ISO MPEG that promises substantially higher compression over H.264/AVC, its previous generation standard completed around 10 years ago. In particular HEVC promises roughly a factor of 2 in compression over H.264 that had delivered a factor of 2 in compression over MPEG-2, its earlier generation standard that had completed another 10 years ago. While AVC is currently dominant having supplemented or displaced MPEG-2 in nearly all digital video applications, services, products, and eco-systems, the time seems ripe for HEVC to displace H.264 in the same manner that H.264 displaced MPEG-2. Overall, MPEG has an excellent history of delivering on video standards that typically result in wide industry adoption.

Intel Media Server Studio (which includes the Intel Media SDK) is a well-known developer product that implements state of art standards based highly optimized decoders, corresponding efficient and highly optimized encoders, file/stream formatting, and pre- and post-processing tools supporting efficient coding. Intel Media Server Studio implements many Codec and tools components initially in software, and later as hybrid (of software and hardware) or entirely in hardware. The reason for this multi-tier approach is faster time to market for software solutions, followed by hybrid solutions that contains partial hardware acceleration, and lastly blazingly fast hardware solutions that scale. Intel Media Server Studio is available both for Windows and Linux. It supports Intel 4th and 5th generation Core and select Xeon Processor based platforms with Intel Iris Pro and Intel HD Graphics.

Intel Media Server Studio includes a number of significant tools, technologies, and enhancements including improved software implementation of HEVC Encoders and Decoders. Since not all HEVC implementations are created equal, this white paper attempts to quantify the quality and performance a developer should expect from Intel Media Server Studio HEVC Codec software implementation.

HEVC Compression Basics

HEVC builds on the well-known classical interframe coding framework of block motion compensated transform coding. However unlike previous MPEG/ITU-T standards including H.264 instead of using smaller, fixed size processing based on macroblocks and blocks for motion compensated prediction and small block transform coding, it uses larger, flexible structures that are partitioned for motion compensated prediction, and a range of large to small block sizes for transform coding. There are other significant difference as well.

HEVC Data Hierarchy

Figure 1 shows high level data structure hierarchy. The terms Video, GOP and Picture as shown are only conceptual while Slices and lower layers are actual layers employed by HEVC.

Figure 1 HEVC data hierarchy. Video, GOP & Pictures are conceptual, others are actual layers.

HEVC Encoder

Fig. 2 shows high level block diagram of HEVC Encoder. Input video frames are partitioned recursively from CTB’s to CUs and then non-recursively into PUs. The prediction partition PUs are then combined to generate Prediction CUs that are differenced from the original resulting in residual CU’s that are recursively QT split into TUs and coded with variable Block Size (VBS) transform of 4×4 (DST or DCT approx.), or 8×8, 16×16, and 32×32 (DCT approx. only). CU/PU Partitioner partitions into CU/PU, and the TU partitioner partitions into TUs. An Encode Controller controls the degree of partitioning performed which depends on quantizer used in transform coding. The CU/PU Assembler and TU Assembler perform the reverse function of partitioner. The decoded (every DPCM encoder incorporates a decoder loop) intra/motion compensated difference partitions are assembled following inverse DST/DCT to which prediction PUs are added and reconstructed signal then Deblock, and SAO Filtered that correspondingly reduce appearance of artifacts and restore edges impacted by coding.

Figure 2 HEVC Encoder

To read the full white paper Deliver High Quality, High Performance HEVC via Intel® Media Server Studio follow the link below.

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