Altera announces Arria 10, 2,666Mbps DDR4 memory FPGA interface

Altera Corporation is demonstrating its Arria 10 DDR4 memory interface operating at an industry-leading 2,666 Mbps.

The Altera’s Arria 10 FPGAs and SoCs are the industry’s only FPGAs available today that support DDR4 memory at these data rates. The new chips deliver a 43 percent improvement in memory performance over previous generation FPGAs and a 10 percent improvement in memory performance over competing 20 nm FPGAs

The design allows hardware designers to use the latest Quartus II software v14.1 to enable 2,666 Mbps DDR4 memory data rates in Arria 10 FPGA and SoC designs. A video demonstration showing the robust memory interface operating at 2,666 Mbps with margin is available below.

Altera chip

Arria 10 FPGAs and SoCs are the industry’s highest performance 20 nm FPGAs and SoCs, offering a one speed-grade advantage over competitive solutions. Supporting the industry’s highest DDR4 memory performance enables communications, computer and storage, and video processing applications to execute high memory bandwidth in their systems, in a cost-effective, low-power manner. Arria 10 FPGA and SoC memory interfaces support today’s high-speed memories, including HMC, DDR4, DDR3, LPDDR3, RLDRAM3, and QDR-IV/ -II+ Xtreme/ -II+/ -II.

“We architected the external memory interfaces in Arria 10 FPGAs and SoCs to provide hardware designers an easy-to-use, high-performance way to get data into and out of the device,” said Raj Patel, senior manager, midrange products, Altera Corporation. "By delivering the industry’s fastest DDR4 data rates we are able to meet our customers' evolving system requirements which are being driven by the tremendous growth in data volume.”

Arria 10 FPGAs and SoCs simplify the development of systems that feature DDR4 memory by integrating a complete physical interface and memory controller into the FPGA. The memory interface is hardened in the FPGA fabric, which delivers higher performance, higher bandwidth and lower power versus a soft implementation.

In addition, a hardened memory interface and controller eliminate the need for designers to use logic resources to build the DDR4 memory interface. Altera's Quartus II software v14.1 includes a DDR4 PHY wizard and controller intellectual property, which further simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.

You might also like...

A Centralized Streaming Gateway For Live SDI Production And IP Distribution

In a time of social distancing, video professionals have turned to technology that allows them to work remotely yet collaboratively over a secure Internet connection. This remote production strategy has helped production and postproduction companies as well as video streaming,…

Essential Guide: High Dynamic Range Broadcasting

HDR offers unbelievable new opportunities for broadcast television. Not only do we have massively improved dynamic range with the potential of eye-watering contrast ratios, but we also have the opportunity to work with a significantly increased color gamut to deliver…

Broadcast For IT - Part 17 - Compression Formats

The bewildering number of video and audio compression formats available is difficult for those new to the industry to come to terms with. For broadcast engineers and IT engineers to work effectively together, IT engineers must understand the formats used,…

Broadcast For IT - Part 16 - Video Compression

To deliver efficient media solutions IT engineers must be able to communicate effectively with broadcast engineers. In this series of articles, we present the most important topics in broadcasting that IT engineers must understand. Here, we look at compression, why,…

FPGA Solutions for Integrating IP and SDI

The coming together of IT and broadcast brings with it a blurred and chaotic interface. As engineers dig deeper into the differences, it becomes apparent that there still is an important role for dedicated hardware.